march 1998 f dn 33 7 n n-channel logic level enhancement mode field effect transistor general description features absolute maximum ratings t a = 25 o c unless other wise noted symbol parameter f dn 33 7 n units v dss drain-source voltage 30 v v gss gate-source voltage - continuous 8 v i d drain/output current - continuous 2.2 a - pulsed 10 p d maximum power dissipation (note 1a ) 0.5 w (note 1 b) 0.46 t j ,t stg operating and storage temperature range -55 to 150 c thermal characteristics r q ja thermal resistance, junction-to-ambient (note 1a) 250 c/w r q jc thermal resistance, junction-to-case (note 1) 75 c/w fdn 33 7n rev.c 2.2 a, 3 0 v, ?r ds(on ) = 0.065 w @ v gs = 4.5 v r ds(on ) = 0.082 w @ v gs = 2.5 v. industry standard outline sot-23 surface mount package using proprietary supersot tm -3 design for superior thermal and electrical capabilities. high density cell design for extremely low r ds(on) . exceptional on-resistance and maximum dc current capability. supersot tm -3 n -c hannel logic level enhancement mode power field effect transistors are produced using fairchild 's proprietary, high cell density, dmos technology. this very high density process is especially tailored to minimize on-state resistance. these devices are particularly suited for low voltage applications in notebook computers, portable phones, pcmcia cards, and other battery powered circuits where fast switching, and low in-line power loss are needed in a very small outline surface mount package. sot-23 supersot t m -8 soic-16 so-8 sot-223 supersot t m -6 g d s supersot -3 tm 337 d s g ? 1998 fairchild semiconductor corporation
electrical characteristics (t a = 25 o c unless otherwise noted ) symbol parameter conditions min typ max units off characteristics bv dss drain-source breakdown voltage v gs = 0 v, i d = 250 a 30 v d bv dss / d t j breakdown voltage temp. coefficient i d = 250 a , referenced to 25 o c 41 mv/ o c i dss zero gate voltage drain current v ds = 24 v, v gs = 0 v 1 a t j = 5 5c 10 a i gssf gate - body leakage, forward v gs = 8 v,v ds = 0 v 100 na i gssr gate - body leakage, reverse v gs = - 8 v , v ds = 0 v -100 na on characteristics (note ) v gs (th) gate threshold voltage v ds = v gs , i d = 250 a 0.4 0.7 1 v d v gs(th) / d t j gate threshold voltage temp. coefficient i d = 250 a , referenced to 25 o c -2.3 mv/ o c r ds(on) static drain-source on-resistance v gs = 4.5 v, i d = 2.2 a 0.054 0.065 w t j =12 5c 0.08 0.11 v gs = 2.5 v, i d = 2 a 0.07 0.082 i d(on) on-state drain current v gs = 4.5 v, v ds = 5 v 10 a g fs forward transconductance v ds = 5 v, i d = 2.2 a 13 s dynamic characteristics c iss input capacitance v ds = 10 v, v gs = 0 v, f = 1.0 mhz 300 pf c oss output capacitance 145 pf c rss reverse transfer capacitance 35 pf switching ch aracteristics (note) t d(on ) turn - on delay time v dd = 5 v, i d = 1 a, v gs = 4.5 v, r gen = 6 w 4 10 ns t r turn - on rise time 10 18 ns t d(off) turn - off delay time 17 28 ns t f turn - off fall time 4 10 ns q g total gate charge v ds = 10 v, i d = 2.2 a, v gs = 4.5 v 7 9 nc q gs gate-source charge 1.1 nc q gd gate-drain charge 1.9 nc drain-source diode characteristics and maximum ratings i s maximum continuous drain-source diode forward current 0.42 a v sd drain-source diode forward voltage v gs = 0 v, i s = 0.42 a (note ) 0.65 1.2 v note: 1 . r q ja is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the s older mounting surface of the drain pins. r q jc is guaranteed by design while r q ca is determined by the user's board design. typical r q ja using the board layouts shown below on fr-4 pcb in a still air environment : scale 1 : 1 on letter size paper 2. pulse test: pulse width < 300 s, duty cycle < 2.0%. fdn 33 7n rev.c a. 250 o c/w when mounted on a 0.0 2 in 2 pad of 2oz cu. b. 270 o c/w when mounted on a 0.001 in 2 pad of 2oz cu.
fdn 33 7n rev.c 0 0.3 0.6 0.9 1.2 1.5 0 1 2 3 4 5 6 v , drain-source voltage (v) i , drain-source current (a) 2.5 v = 4.5v gs 2.0 1.5 ds d 3.0 0 1 2 3 4 5 6 0.8 1 1.2 1.4 1.6 1.8 2 i , drain current (a) drain-source on-resistance v = 2.0v gs 3.5 3.0 4.5 d 2.5 r ds(on ) , normalized typical electrical characteristics figure 1. on-region characteristics . figure 2. on-resistance variation with drain current and gate -50 -25 0 25 50 75 100 125 150 0.6 0.8 1 1.2 1.4 1.6 t , junction temperature (c) drain-source on-resistance j v = 4.5 v gs i = 2.2a d r , normalized ds(on) figure 3. on-resistance variation with temperature . 0 0.5 1 1.5 2 2.5 0 1 2 3 4 5 6 7 v , gate to source voltage (v) i , drain current (a) 25c 125c v = 5.0v ds gs d t = -55c j figure 5 . transfer characteristics. 0 0.2 0.4 0.6 0.8 1 0.0001 0.001 0.01 0.1 0.5 2 4 v , body diode forward voltage (v) i , reverse drain current (a) t = 125c j 25c -55c v = 0v gs sd s figure 4 . on-resistance variation with gate-t o -source voltage. 1 2 3 4 5 0 0.05 0.1 0.15 0.2 0.25 v , gate to source voltage (v) gs r , on-resistance (ohm) ds(on) 125c 25c i = 1.1a d
fdn 33 7n rev.c 0 2 4 6 8 0 1 2 3 4 5 q , gate charge (nc) v , gate-source voltage (v) g gs i = 2.2a d 15v v = 5v ds 10v 0.1 0.5 1 2 5 10 20 50 0.01 0.03 0.1 0.3 1 2 5 10 20 v , drai n-source voltage (v) i , drain current (a) ds d dc 1s 100ms 10s 1ms rds(on) limit v = 4.5v single pulse r =250 c/w t = 25c gs a q ja 10ms 0.0001 0.001 0.01 0.1 1 10 100 300 0 10 20 30 40 50 single pulse time (sec) power (w) single pulse r =270 c/w t = 25c q ja a figure 10 . single pulse maximum power dissipation. figure 11 . transient thermal response curve . thermal characterization performed using the conditions described in note 1b . transient thermal response will change depending on the circuit board design. 0.1 0.2 0.5 1 2 5 10 20 20 50 100 200 500 1000 v , drain to source voltage (v) capacitance (pf) ds c iss f = 1 mhz v = 0v gs c oss c rss figure 8. capacitance characteristics . figure 7 . gate charge characteristics. figure 9. maximum safe operating area. typical electrical characteristics (continued) 0.0001 0.001 0.01 0.1 1 10 100 300 0.001 0.002 0.005 0.01 0.02 0.05 0.1 0.2 0.5 1 t , time (sec) transient thermal resistance r (t) = r(t) * r r = 270 c/w duty cycle, d = t /t 1 2 q ja q ja q ja t - t = p * r (t) q ja a j p(pk) t 1 t 2 r(t), normalized effective 1 single pulse d = 0.5 0.1 0.05 0.02 0.01 0.2
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